[57] SpARC: Token Similarity-Aware Sparse Attention Transformer Accelerator via Row-wise Clustering
Han Cho, Dongjun Kim, Seung-Eon Hwang, and Jongsun Park | ACM/IEEE Design Automation Conference (DAC), June. 2024.
[56] HeNCoG: a Heterogeneous Near-Memory Computing Architecture for Energy Efficient GCN Acceleration
Seung-Eon Hwang, Duyoung Song, and Jongsun Park | IEEE International Symposium on Circuits and Systems (ISCAS), May. 2024.
[55] Identifying Unnecessary 3D Gaussians using Clustering for Fast Rendering of 3D Gaussian Splatting
Joongho Jo, Hyeongwon Kim, and Jongsun Park | arXiv.org, 21 Feb. 2024
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[54] Low-Cost 7T-SRAM Compute-In-Memory design based on Bit-Line Charge-Sharing based Analog-To-Digital Conversion
Kyeongho Lee, Joonhyung Kim and Jongsun Park | IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2022.
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[53] A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processing
Joonhyung Kim, Kyeongho Lee, Jongsun Park | ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2022.
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[52] A Time-to-first-spike Coding and Conversion Aware Training for Energy-Efficient Deep Spiking Neural Network Processor Design
Dongwoo Lew, Kyungchul Lee, and Jongsun Park | ACM/IEEE Design Automation Conference (DAC), Jul. 2022.
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[51] A 10T SRAM Compute-In-Memory Macro with Analog MAC Operation and Time Domain Conversion
Hyunchul Park, Kyeongho Lee, Jongsun Park | IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), June 2022.
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[50] BiMDiM: Area efficient Bi-directional MRAM Digital in-Memory Computing
Dongsu Kim, Yunho Jang, Taehwan Kim, Jongsun Park | IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), June 2022.
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[49] A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration
Kyeongho Lee, Sungsoo Cheon, Joongho Jo, Woong choi, and Jongsun Park | ACM/IEEE Design Automation Conference (DAC), Dec. 2021.
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[48] An Energy-Efficient SNN Processor Design based on Sparse Direct Feedback and Spike Prediction
Seunghwan Bang, Dongwoo Lew, Sunghyun Choi, and Jongsun Park | International Joint Conference on Neural Networks (IJCNN), July 2021.
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[47] Low Cost Heterogeneous Aria S-Box Implementation for CPA-Resistance
Junghoon Cho, Junhyun Song, and Jongsun Park | IEEE International Symposium on Circuits and Systems (ISCAS), May 2021.
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[46] Low Energy Domain Wall Memory Based Convolution Neural Network Design with Optimizing Mac Architecture
Jooyoon Kim, Yunho Jang, Taehwan Kim, and Jongsun Park | IEEE International Symposium on Circuits and Systems (ISCAS), May 2021.
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[45] Prediction Confidence based Low Complexity Gradient Computation for Accelerating DNN Training
Dongyeob Shin, Geonho Kim, Joongho Jo, and Jongsun Park | ACM/IEEE Design Automation Conference (DAC), July 2020.
[44] Bit Parallel 6T SRAM In-Memory Computing with Reconfigurable Bit-Precision
Kyeongho Lee, Jinho Jeong, Sungsoo Cheon, Woong choi, and Jongsun Park | ACM/IEEE Design Automation Conference (DAC), July 2020.
[43] Dynamic Reference based Early Write Termination for Low Energy SOT-MRAM
Taehwan Kim, Eunjong Yeo, Yunho Jang, Yeongkyo Seo, and Jongsun Park | IEEE International Symposium on Circuits and Systems (ISCAS), May 2020.
[42] An Energy-efficient On-chip Learning Architecture for STDP based Sparse Coding
Heetak Kim, Hoyoung Tang, and Jongsun Park | ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), July. 2019.
[41] Sensitivity based Error Resilient Techniques for Energy Efficient Deep Neural Network Accelerators
Wonseok Choi, Dongyeob Shin, Jongsun Park, and Swaroop Ghosh | ACM/IEEE Design Automation Conference (DAC), Jun. 2019.
[40] Low Cost Ternary Content Addressable Memory based on Early Termination Precharge Scheme
Kyeongho Lee, Geon Ko, and Jongsun Park | IEEE International Symposium on Circuits and Systems (ISCAS), May 2019.
[39] Low Cost Hardware Implementation of LEA-128 Encryption using Bit-Serial Technique
Byungjun Choi, Bohun Kim, and Jongsun Park | IEEE International SOC Conference (ISOCC), Nov. 2018.
[38] Spin Orbit Torque-RAM Write Energy Reduction with Self-Verification Scheme
Taehwan Kim, and Jongsun Park | IEEE International SOC Conference (ISOCC), Nov. 2018.
[37] Novel Fault Tolerant Techniques for Resilient Deep Neural Network Accelerators
Dongyeob Shin, Jongsun Park, Swaroop Ghosh | IBM/IEEE AI Compute Symposium, Oct. 2018.
[36] Test Methodologies for Supervised Machine Learning Accelerators
Seyedhamidreza Motaman, Swaroop Ghosh, Jongsun Park | IBM/IEEE AI Compute Symposium, Oct. 2018.
[35] Spin Orbit Torque Device based Stochastic Multi-bit Synapses for On-chip STDP learning
Gyuseong Kang, Yunho Jang, and Jongsun Park | ACM/IEEE International Symposium of Low Power Electronics Design (ISLPED) - Best Paper Nominee, July 2018.
[34] Spike Counts Based Low Complexity Learning with Binary Synapse
Hoyoung Tang, Heetak Kim, Donghyeon cho and Jongsun Park | International Joint Conference on Neural Networks (IJCNN), July 2018.
[33] Half-and-Half Compare Content Addressable Memory with Charge-Sharing based Selective Match-Line Precharge Scheme
Woong Choi, Hoonki Kim, Changnam Park, Taejoong Song and Jongsun Park | IEEE Symposium on VLSI Circuits (VLSIC), Jun. 2018.
[32] Content Addressable Memory Based Binarized Neural Network Accelerator Using Time-Domain Signal Processing
Woong Choi, Kwanghyo Jeong, Kyungrak Choi, Kyeongho Lee and Jongsun Park | ACM/IEEE Design Automation Conference (DAC), Jun. 2018.
[31] Low Cost Ternary Content Addressable Memory Using Adaptive Matchline Discharging Scheme
Woong Choi, Kyeongho Lee and Jongsun Park | IEEE International Symposium on Circuits and Systems (ISCAS), May 2018.
[30] Charge-Recycling based Redundant Write Prevention Technique for Low Power SOT-MRAM
Gyuseong Kang, Yunho Jang and Jongsun Park | IEEE International Symposium on Circuits and Systems (ISCAS), May 2018.
[29] An Efficient Convolutional Neural Networks Design with Heterogeneous SRAM Cell Sizing
Wonseok Choi and Jongsun Park | IEEE International SOC Conference (ISOCC), Nov. 2017.
[28] Bit-width Reduction and Customized Register for Low Cost Convolutional Neural Network Accelerator
Kyungrak Choi, Woong Choi, Kyungho Shin, and Jongsun Park | ACM/IEEE International Symposium on Low Power Electronics Design (ISLPED), July 2017.
[27] A DRAM based Physical Unclonable Function Capable of Generating > 1032 Challenge Response Pair per 1Kbit Array for Secure Chip Authentication
Qianying Tang, Chen Zhou, Woong Choi, Gyuseong Kang, Jongsun Park, Keshab Parhi, and Chris H. Kim | IEEE Custom Integrated Circuits Conference (CICC), Apr. 2017.
[26] Customized SRAM design for Low Power Video codec applications
Sangkyu Lee, Hoyoung Tang, Kyungrak Choi, and Jongsun Park | IEEE International SOC Conference (ISOCC), Oct. 2016.
[25] A Compact Multi-Mode CORDIC with Global-Shifting-Sum (GSS) Method
Gihoon Jung, Kyungrak Choi, and Jongsun Park | IEEE Asia Pacific Conference on Circuits & Systems (APCCAS), Oct. 2016.
[24] Domain Wall Memory based Convolutional Neural Networks for Bit-width Extendability and Energy-Efficiency
Jinil Chung, Jongsun Park, and Swaroop Ghosh | ACM/IEEE International Symposium on Low Power Electronics (ISLPED), Aug. 2016.
[23] A Inversion-Less Peterson algorithm based shared KES architecture for Concatenated BCH decoder
Seungyong An, Hoyoung Tang, and Jongsun Park | IEEE International SOC Conference (ISOCC), Nov. 2015.
[22] Low Complexity Massive MIMO Detection Architecture based on Neumann Method
Byunggi Kang and Jongsun Park | IEEE International SOC Conference (ISOCC), Nov. 2015.
[21] Domain Wall Memory based Digital Signal Processors for Area and Energy-Efficiency
Jinil Chung, Kenneth Ramclam, Swaroop Ghosh, and Jongsun Park | ACM/IEEE Design Automation Conference (DAC), June 2015.
[20] Self-Correcting STTRAM under Magnetic Field Attacks
Jae-Won Jang, Jongsun Park, Swaroop Ghosh, and Swarup Bhunia | ACM/IEEE Design Automation Conference (DAC), June 2015.
[19] A Hybrid Multimode BCH Encoder Architecture for Area Efficient Re-Encoding Approach
Hoyoung Tang, Gihoon Jung, and Jongsun Park | IEEE International Symposium on Circuits and Systems (ISCAS), May. 2015.
[18] Dynamic Stability Estimation for Latch-Type Voltage Sense Amplifier
Woong Choi, Jongsun Park, and Gyuseong Kang | IEEE International SOC Conference (ISOCC), Nov. 2014.
[17] Gram-Schmidt tailed High-throughput QR Decomposition Architecture for MIMO detector
Dongyeob Shin, Ji-Hwan Yoon, Jongsun Park, and Woong Choi | IEEE International SOC Conference (ISOCC), Nov. 2014.
[16] A Low-Complexity Composite QR Decomposition Architecture for MIMO Detector
Ji-Hwan Yoon, Dongyeob Shin, and Jongsun Park | IEEE International Symposium on Circuits and Systems (ISCAS), June 2014.
[15] Reconfigurable ECC for Adaptive Protection of Memory
Abhishek Basak, Yu Zheng, Jangwon Park, Jongsun Park, and Swarup Bhunia | IEEE Midwest Symposium on Circuits and Systems (MWSCAS), August 2013.
[14] Multidimensional Householder based High-Speed QR Decomposition Architecture For MIMO Receivers
Iput Heri Kurniawan, Ji-Hwan Yoon, and Jongsun Park | IEEE International Symposium on Circuits and Systems (ISCAS), May 2013.
[13] Dual Queue based Rate Selecting Schedule for Throughput Enhancement in WLANs
Dongwan Kim, Wan-Seon Lim, and Jongsun Park | IEEE International Symposium on Circuits and Systems (ISCAS), pp. 540-543, May 2012.
[12] High-Speed Tournament Givens Rotation-based QR Decomposition Architecture for MIMO reciever
Min-Woo Lee, Ji-Hwan Yoon, and Jongsun Park | IEEE International Symposium on Circuits and Systems (ISCAS), pp. 21-24, May 2012.
[11] Variation-aware low-power video processor design techniques
Woojin Rim, Jinmo Kwon, and Jongsun Park | IEEE Midwest Symposium on Circuits and Systems (MWSCAS), 2011.
[10] Improved MIMO SIC Detection Exploiting ML Criterion
Ji-Woong Choi, Jungwon Lee, Hui-Ling Lou, and Jongsun Park | IEEE Vehicular Technology Conference (VTC), Fall, 2011.
[9] Digital Signal Processing in Bio-implantable Systems: Design Challenge and Emerging solutions
Seetharam Narasimhan, Jongsun Park, and Swarup Bhunia | Asia Symposium on Quality Electronics Design (ASQED), 2010.
[8] Dynamic Bit Width Adaptation in DCT : Image Quality versus Computation Energy Trade off
Jongsun Park, Jung Hwan Choi, and Kaushik Roy | Design, Automation and Test in Europe (DATE), 2006.
[7] Hardware Architecture and VLSI Implementation of a low-power high-performance polyphase channelizer with application to subband adaptive filtering
Yongtao Wang, Hamid Mahmoodi, Hunsoo Choo, Jongsun Park, Woopyo Jeong, Lihyih Chiou and Kaushik Roy | IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Volume 5, pp 97-100, May, 2004.
[6] A low power reconfigurable DCT architecture to trade off image quality for computational complexity
Jongsun Park and Kaushik Roy | IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), May 2004.
[5] Efficient Generation of 1/fα Noise Using a Multi-rate Filter Bank
Jongsun Park, Khurram Muhammad and Kaushik Roy | IEEE Custom Integrated Circuit Conference (CICC), pp 707-710, September, 2003.
[4] High performance and Low power FIR filter Design Based on Sharing Multiplication
Jongsun Park, Woopyo Jeong, Hunsoo Choo, Hamid Mahmoodi, Yongtao Wang, Kaushik Roy | IEEE International Symposium on Low Power Electronics Design (ISLPED), pp 295-300, August, 2002.
[3] DCT Processor Architecture Based on Computation Sharing
Soonkeon Kwon, Jongsun Park and Kaushik Roy | IEEE International Conference on Circuits and Systems for Communications, pp 162-165, June, 2002.
[2] Low Power Reconfigurable DCT Design based on Sharing Multiplication
Jongsun Park, Soonkeon Kwon, Kaushik Roy | IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Vol.3, pp.3116-3119, June, 2002.
[1] Non adaptive and Adaptive Filter implementation based on sharing multiplication
Jongsun Park, Hunsoo Choo, Khurram Muhammad, Kaushik Roy | IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Volume 1, pp 460-463, June 2000.
[40] Implementation of ARIA - 128 Hardware Using Bit-Serial Based Dataflow Modification
Junghoon Cho, Joongho Jo and Jongsun Park | 2020 대한전자공학회 하계종합학술대회, Aug. 2020.
[39] Conversion Based Low Operation SNN Implementation with Runtime Threshold Adaptation and Neuron Pruning
Sunghyun Choi, Dongwoo Lew, Hyeonseong Kim, Geonho Kim and Jongsun Park | 2020 대한전자공학회 하계종합학술대회, Aug. 2020.
[38] Spike Counts based Early Termination Scheme for Low Latency Neuromorphic Hardware
Geonho Kim, Taehwan Kim, Seunghwan Bang, Hoyoung Tang and Jongsun Park | 한국반도체학술대회, Feb. 2020.
[37] High Speed HIGHT Block Cipher Hardware Design
Byungjun Choi, Bohun Kim, Junghoon Cho and Jongsun Park | 한국반도체학술대회, Feb. 2020.
[36] Low Area Folded Threshold Implementation without Latency Loss
Byungjun Choi, Bohun Kim and Jongsun Park | 2019 SoC 학술대회, May 2019
[35] Low Power and Low Area SOT-MRAM using Voltage Controlled Magnetic Anisotropy
Eunjong Yeo and Jongsun Park | 2019 SoC 학술대회, May 2019
[34] A Low-Latency and Low-Power RS Decoder that pre-corrects a small number of errors
Geonho Kim, Dongyeob Shin and Jongsun Park | 2019 SoC 학술대회, May 2019
[33] An Energy-efficient On-chip learning Architecture for STDP based Sparse Coding
Mingi Kim and Jongsun Park | 2019 SoC 학술대회, May 2019
[32] Approximation Schemes for Energy Efficient Spike-based Computing System
Hyeonseong Kim and Jongsun Park | 한국반도체학술대회, Feb. 2019.
[31] Processing In-Memory of BCH encoder using a 9T SRAM Array with XOR/Write-Back/SHIFT operation
Geon Ko, Taehwan Kim, Kyeongho Lee, Yunho Jang, and Jongsun Park | 한국반도체학술대회, Feb. 2019.
[30] Low-area ARIA hardware implementation with optimization of single round function
Junghoon Cho and Jongsun Park | 2018 한국전기전자학회 하계학술대회, Aug 2018.
[29] Low Power Content Addressable Memory using Negative Voltage Generator
Geon Ko, Kyeongho Lee, and Jongsun Park | 2018 한국전기전자학회 하계학술대회, Aug 2018.
[28] An Energy-efficient Convolutional Neural Network Using Zero Computation Reduction
Daehan Ji, Bohun Kim, and Jongsun Park | 2018 SoC 학술대회, May 2018.
[27] Designing Energy Efficient High Accuracy Spiking Neural Network using Approximate Computing
Heetak Kim and Jongsun Park | 2018 SoC 학술대회, May 2018.
[26] An Energy-efficient and Low area CNN Accelerator based on Combined Weight Type Quantization
Nahsung Kim, Dongyeob Shin, Wonseok Choi, Bohun Kim, and Jongsun Park | 한국반도체학술대회, Feb. 2018.
[25] Energy efficient Spike-Timing Dependent Plasticity Rule for Unsupervised Learning
Donghyeon Cho, Gyuseong Kang, Heetak Kim, Yunho Jang, and Jongsun Park | 한국반도체학술대회, Feb. 2018.
[24] Low Power Contents Addressable Memory with NMOS Gated Selective Precharge Matchline
Kwanghyo Jeong, Kyeongho Lee, Woong Choi, and Jongsun Park | 한국반도체학술대회, Feb. 2018.
[23] Approximate Computation Sharing Multiplier for Low Power Convolutional Neural Networks Design
Cheolhwan Kim, Gyuseong Kang and Jongsun Park | 한국반도체학술대회, Feb. 2017.
[22] Low Power Embedded SRAM for Pipelined Bitonic Sorter
Kyungrak Choi, Jinil Chung, Hoyoung Tang, Woong Choi, and Jongsun Park | 2016 대한전자공학회 하계종합학술대회, Jun. 2016.
[21] Retention-aware Reconfigurable eDRAM-based LIFO Memory Design for DSP System
Cheolhwan Kim, Byeongil Park, Gyuseong Kang, and Jongsun Park | 2016 대한전자공학회 하계종합학술대회, Jun. 2016.
[20] Low Power SRAM for FFT Processor with preventing unnecessary Pseudo-Read and Wordline activation
Kyungrak Choi, Hoyoung Tang, Woong Choi, and Jongsun Park | 2016 SoC 학술대회, May. 2016.
[19] Retention-Time Aware Reconfigurable eDRAM-based FIFO Memory for Refresh-Free DSP Design
Byeonggil Park, Gyuseong Kang, and Jongsun Park | 한국반도체학술대회, Feb. 2016.
[18] A Low Complexity Massive MIMO Detection Architecture based on Richardson Iterative Method
Dongyeob Shin, Ji-Hwan Yoon, Gihoon Jung, and Jongsun Park | 한국반도체학술대회, Feb. 2016.
[17] Unnecessary Pseudo-Read Prevent SRAM for Low-Power Viterbi Decoder
Woong Choi, Kyungho Shin, and Jongsun Park | 한국반도체학술대회, Feb. 2016.
[16] A Single-Ended 6T1D SRAM Cell With Feedback-fade Write Access for Near-threshold Operation
Kyungho Shin and Jongsun Park | 2015 추계학술대회.
[15] An Area Efficient Scaling-Free CORDIC Algorithm Using Global Shifting Sum(GSS) Method
Gihoon Jung and Jongsun Park | 한국반도체학술대회, Feb. 2015.
[14] A MP-based BCH Encoder for Reducing the Latency of SC based on re-Encoding Architecture
Hoyoung Tang and Jongsun Park | 한국반도체학술대회, Feb. 2015.
[13] Low Power Signal Processing Unit for Pulse Oximetry
Gyuseong Kang and Jongsun Park | 한국반도체학술대회, Feb. 2015.
[12] Unified Single-port Survivor Memory for High-speed Viterbi Decoder using 3-unit Packing/Unpacking-based Data Processing
Jinil Chung and Jongsun Park | 한국반도체학술대회, Feb. 2014.
[11] Hardware Optimization for Low Complexity Edge Detection
Juseong Lee and Jongsun Park | 한국반도체학술대회, Feb. 2014.
[10] Heterogeneous Precharge Level을 이용한저전력 H.264용 임베디드 SRAM 설계
송동후, 이주성, 신동엽, 박종선 | 2013 대한전자공학회 하계종합학술대회.
[9] Write 동작의 에너지 감소를 통한 Viterbi decoder전용 저전력 임베디드 SRAM 설계
당호영, 송동후, 신동엽, 박종선 | 2013 SoC 학술대회.
[8] A Single-Ended 6T SRAM Cell with Read-Upset-Preventor
Samir Debnath, Woong Choi, and Jongsun Park | 2012 추계학술대회.
[7] Low Power CORDIC Architecture Using Trigonometric Characteristics
이민우, 박종선 | pp.365-366, 2012 반도체 학술대회.
[6] 저전력 H.264 프로세서를 위한 가변적인 비트 폭임베디드 메모리 설계
박장원, 권진모, 김동완, 박종선 | pp. 302-303, 2012 반도체 학술대회.
[5] 알고리즘적인 재공식화를 통한 저전력 LDPC 복호기의 설계
윤지환, 박종선 | 2011 추계학술대회.
[4] 저전력 H.264 프로세서를 위한 이종 사이즈 임베디드 메모리설계
권진모, 박종선 | 2011 SoC 학술대회.
[3] 저전력 H.264/AVC의 어플리케이션을 위한 중요도 기반 에러 보정부호화 방안
이인수, 박종선 | 2010 추계학술대회.
[2] An Energy-Efficient Reconfigurable DLMS Adaptive Filter Design
이석재, 이민우, 최지웅, 박종선 | 2010 SoC 학술대회.
[1] High Performance CORDIC Architecture using Sign-Select Lookahead Approach
이민우, 박종선 | 제17회 한국반도체학술대회, 2010.
