SRAM & eDRAM

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The embedded memories in current digital processors are a way larger than that of the data paths. The static random access memory (SRAM) design team had been trying to design reliable on-chip memory systems with lowering the cost of memories (power, performance, area, yield). In recent years, the rapid growth of data-intensive applications (AI, real-time visual processing, etc.) have made data movement issue become one of the largest bottlenecks in computing system (the memory wall problem). To reduce the data movement between computing units and embedded memories, Compute-In-Memory (CIM) has been introduced. CIM can provide massive parallelism by dividing computation workload with computing units, thus reducing the amount of data movement. Recently, our research team is focusing on the Compute-In-Memory (CIM) SRAM for energy efficient data-intensive applications. The following are research topics we are interested in.

• Novel SRAM bitcell / assist circuit / architecture design for performance and yield improvement
• Compute-In-Memory SRAM design for data intensive application (AI, Automotive driving, HPC)
• Application-specific embedded memory design (eDRAM, TCAM, FIFO)

Emerging Memories

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In current digital processors, the size of the embedded memories in a chip are a way larger than that of the data paths. The CMOS based memories, such as static random access memory (SRAM), have been widely used as the embedded memories. But, SRAMs are suffering from large static power consumption, thus becoming a main bottleneck of CMOS device scaling. Spin-orbit torque MRAM (SOT-MRAM) have emerged as one of the possible candidates to substitute or assist SRAM. The SOT-MRAM design team’s efforts are focused on designing reliable SOT-MRAM with improving the memory costs in terms of write energy, speed, and area. The SOT devices can be also effectively used to implement Artificial Neural Network Hardwares for running bio-inspired spiking neural network algorithms.

• Our current research focuses
• Circuit design for SOT-MRAM with energy efficient, robust, low area and high performance.
• Circuit-level, Architecture-level designs on Artificial Neural Network Hardware using emerging device.
• Circuit design on various non-volatile logic component.